1. Field of the Invention
The present invention relates to a clock generator which generates clock signals.
2. Description of Related Art
FIG. 1 is a schematic diagram of a clock generator. The clock generator CG is configured so as to input an input clock signal A and a reference signal B, and output an output clock signal C. Specifically, as shown in a timing chart of the timing relationship of the input clock signal A, the reference signal B and the output clock signal C, the clock generator CG outputs the input clock signal A, which is asynchronous with the reference signal B, as the output clock signal C in synchronism with the rising timing (or falling timing) of the reference signal B.
FIG. 3 is a logical circuit diagram showing a configuration example of this kind of clock generator.
The input clock A is inputted to an inverter I.sub.1A and an input terminal D of a D flip-flop DF.sub.1. An output signal of the inverter I.sub.1A is inputted to one input terminal of a NAND circuit N.sub.1 and an inverter I.sub.1B. An output signal from an output terminal Q of the D flip-flop DF.sub.1 is inputted to one input terminal of an AND circuit AN.sub.1, and all output signal of the AND circuit AN.sub.1 is inputted to the other input terminal of the NAND circuit N.sub.1. All output signal of the NAND circuit N.sub.1 is inputted to a first input terminal a.sub.1 of a multi-input AND circuit AN.sub.0. An output signal of the inverter I.sub.1B is inputted to an inverter I.sub.2A and an input terminal D of a D flip-flop DF.sub.2. An output signal of the inverter I.sub.2A is inputted to one input terminal of a NAND circuit N.sub.2 and an inverter I.sub.2B.
An output signal from an output terminal Q of the D flip-flop DF.sub.2, is inputted to one input terminal of an AND circuit AN.sub.2. An output signal of the AND circuit AN.sub.2 is inputted to the other input terminal of the NAND circuit N.sub.2, and an output signal of the NAND circuit N.sub.2 is inputted to a second input terminal a.sub.2 of the multi-input AND circuit AN.sub.0. An inverted output signal from an inverted output terminal #Q of the D flip-flop DF.sub.2 is inputted to the other input terminal of the AND circuit AN.sub.1. An output signal of the inverter I.sub.2B is inputted to an inverter I.sub.3A and an input terminal D of a flop-flop DF.sub.3. An output signal of the inverter I.sub.3A is inputted to an inverter I.sub.3B and one input terminal of a NAND circuit N.sub.3. An output signal of the NAND circuit N.sub.3 is inputted to a third input terminal a.sub.3 of the multi-input AND circuit AN.sub.0. An output signal from an output terminal Q of the D flip-flop DF.sub.3 is inputted to one input terminal of an AND circuit AN.sub.3. An output signal of the AND circuit AN.sub.3 is inputted to the other input terminal of the NAND circuit N.sub.3. An inverted output signal from an inverted output terminal #Q of the D flip-flop DF.sub.3 is inputted to the other input terminal of the AND circuit AN.sub.2. To each trigger terminal T of the D flip-flop DF.sub.1, DF.sub.2, DF.sub.3 is inputted commonly the reference signal B.
As a result, the output clock signal C is outputted from the multi-input AND circuit AN.sub.0. A unit circuit U.sub.1 (U.sub.2, U.sub.3) is composed of the inverter I.sub.1A (I.sub.2A, I.sub.3A), the inverter I.sub.1B (I.sub.2B, I.sub.3B), the D flip-flop DF.sub.1 (DF.sub.2, DF.sub.3), the AND circuit AN.sub.1 (AN.sub.2, An.sub.3) and the NAND circuit N.sub.1 (N.sub.2, N.sub.3). In FIG. 3, a state in which the unit circuits U.sub.1, U.sub.2 and U.sub.3 are connected in cascade is shown. In the actual circuit, a plurality of unit circuits each the same as the unit circuits U.sub.1, U.sub.2 and U.sub.3 are connected in cascade.
Next, an operation of the conventional clock generator configured as mentioned above is described referring to a timing chart of the relationship among each signal shown in FIG. 4.
When the input clock signal A is inputted to the clock generator, it is transmitted through the inverter I.sub.1A, I.sub.1B, I.sub.2A, I.sub.2B, I.sub.3A, I.sub.3B . . . successively. In general, in a case where a clock signal is inputted to an inverter, the inverter outputs the clock signal with slight delay because the inverter has a delay time of a gate operation.
Therefore, a phase delay of the input clock signal A accumulates by a slight delay at every passage through inverter, the phase of the clock at a node M.sub.1 to which a signal is outputted from the inverter I.sub.1B, at a node M.sub.2 to which a signal is outputted from the inverter I.sub.2B, and at a node M.sub.3 to which a signal is outputted from the inverter I.sub.3B is delayed successively.
When the reference signal B rises, each D flip-flop DF.sub.1, DF.sub.2, DF.sub.3 . . . latches simultaneously a value of the input clock signal A whose phase at each node M.sub.1, M.sub.2, M.sub.3 . . . is slightly delayed. By this operation, each D flip-flop latches data of "H" or "L". Therefore, the following state occurs: between adjacent two D flip-flops a latch data of the D flip-flop positioned at the upstream side of the input clock signal A becomes "H", and a latch data of the D flip-flop positioned at the downstream side of the input clock signal A becomes "L". For example, when the D flip-flop DF.sub.2 latches data of "H" and the D flip-flop DF.sub.3 latches data of "L", an inverted output signal having "H" level is inputted to the AND circuit AN.sub.2, so that the output signal of the AND circuit AN.sub.2 becomes "H". By this reason, the NAND circuit N.sub.2 to which the output signal of the AND circuit AN.sub.2 is inputted enters a state in which the clock signal can be transmitted.
As described above, the state in which the latch data of the D flip-flop positioned at the upstream side of the input clock signal A becomes "H" and the latch data of the D flip-flop positioned at the downstream side of the input clock signal A becomes "L" occurs at plural positions because the input clock A is delayed slightly at every passage through the inverter. Therefore, the number of NAND circuits which enter a state in which the clock signal can be transmitted increases. On the other hand, in the case where both latch data of the adjacent two D flip-flops are "H", the output signal of the AND circuit to which abovementioned two latch data are inputted becomes "L", so that the output signal of the NAND circuit to which the output signal of abovementioned AND circuit is inputted is fixed to "H". By such a manner, a number of NAND circuits have output signals which are fixed to "H". Then, intermediate signals A1, A2, A3 . . . which are the output signals of abovementioned NAND circuits are inputted to the multi-input AND circuit AN.sub.0, so that the output clock C rises at the time point when the logic of the intermediate signals from the plural NAND circuits which can transmit the input clock signal A is established, and the output clock signal falls at the time point when the logic is not established. As a result, an output clock signal C in synchronism with the reference signal B is generated.
Now, in the abovementioned conventional clock generator, the output clock signal rises at the time point when the logic of the plural intermediate signals outputted corresponding to the input clock from the NAND circuits which enter the state in which it is possible to transmit a clock signal is established. Therefore, in the case where the number of the intermediate signals outputted corresponding to the input clock increases, the establishing timing of the logic delays more and more. As mentioned above, however, the higher the frequency of the input clock signal becomes, the more the positions, between the adjacent two D flip-flops, at which data "H" is latched by the D flip-flop of the upstream side and data "L" is latched by the D flip-flop of the downstream side increase, so that the number of intermediate signals outputted from the unit circuits based on these latch data increases. Consequently, the higher the frequency of the input clock signal becomes, the more the rising timing of the clock delays, thereby the duty for the frequency of the output clock becomes small. Therefore, when a CPU is driven by the generated output clock signal of the conventional clock generator, there is a fear that the CPU malfunctions because of short margin according to frequencies of the input clock signal.